This invention relates to microelectronic manufacturing methods and devices, and more particularly to silicon ingot manufacturing methods and silicon ingots and wafers manufactured thereby.
Monocrystalline silicon, which is the starting material in fabricating semiconductor devices, is grown into a cylindrical ingot by a crystal growth technique, which is referred to as the Czochralski (CZ) technique. The ingot of monocrystalline silicon is processed into wafers via a series of wafering processes such as slicing, etching, cleaning, polishing and the like. According to the CZ technique, a seed crystal of monocrystalline silicon is immersed into molten silicon and pulled upwards, and the molten silicon is then grown into a monocrystalline ingot by slow extraction. The molten silicon is contained in a quartz crucible, and is contaminated with a variety of impurities, one of which is oxygen. At the melting temperature of silicon, the oxygen permeates the crystal lattice until it reaches a predetermined concentration which generally is determined by the solubility of oxygen in silicon at the melting temperature of silicon and by the actual segregation coefficient of oxygen in solidified silicon. The concentration of oxygen, which permeates the silicon ingot during crystal growth, is greater than the solubility of oxygen in solidified silicon at typical temperatures used in semiconductor device manufacture. As the crystal grows from the molten silicon and cools, the solubility of oxygen therein rapidly decreases, whereby oxygen is saturated in the cooled ingot.
The ingot is sliced into wafers. The remaining interstitial oxygen in the wafers is grown to oxygen precipitates during subsequent thermal processes. The presence of oxygen precipitates in the device active region may degrade the gate oxide integrity and/or may cause undesirable substrate leakage current. However, if they are present outside the device active region (i.e. in the bulk region), they can getter metallic impurities that arise from device processing. This desirable function is referred to as gettering.
FIG. 1 is a sectional view of a conventional Metal Oxide Semiconductor (MOS) transistor. Referring to FIG. 1, when the oxygen precipitates at the wafer surface exist in a channel region, which is located in an active region of the semiconductor device between a source region 12 and a drain region 14 which are formed near the surface of a silicon substrate 10, a gate insulation layer 16, for electrically insulating a gate electrode 18 and the silicon substrate 10, may break down. In addition, the refresh characteristics of a memory device that uses the MOSFET may degrade.
Also, oxygen precipitates formed in the bulk region 10a of the wafer, which are produced by subsequent heat treatment, can act as a leakage source and can act as intrinsic gettering sites, which are capable of trapping unfavorable metal contaminants during subsequent semiconductor device manufacturing. Thus, if the concentration of oxygen in the ingot is high, the concentration of oxygen precipitates which act as the intrinsic gettering sites can increase, so that the gettering capability increases. However, if the concentration of oxygen is not sufficient, oxygen precipitates may not be produced in the bulk region, so that the gettering capability may be reduced or may not be present at all. Thus, it may be desirable to properly control the amount of oxygen precipitates distributed in the bulk region of the wafer.
In a wafer which is obtained by a conventional crystal growth and wafering process, oxygen precipitates distribute through the wafer, from the top (front side) surface of the bottom (back side) surface. In general, a Denuded Zone (DZ) 10b should be provided from the top surface to a predetermined depth, which is devoid of D-defects (vacancy agglomerates), dislocations, stacking faults and oxygen precipitates. However, wafers fabricated by conventional methods may produce oxygen precipitates near the surface of the wafer, which can act as a source of leakage current.
Thus, in order to form intrinsic gettering sites in the bulk region of the wafer with a sufficient DZ near the surface of the wafer, a wafer containing a high concentration of oxygen, for example, at an initial oxygen concentration of 13 parts per million atoms (ppma) or more may be thermally processed for a long period of time by alternating the temperature between low and high levels, such that oxygen precipitates may be generated in the bulk region of the wafer. However, it may be difficult to obtain sufficient DZ because the DZ may strongly depend on the out-diffusion of interstitial oxygen. In a semiconductor wafer thermally processed by this conventional technique, the oxygen precipitate concentration profile through the wafer, from the top surface to the bottom surface of the wafer, may be as illustrated in FIG. 2.
Particularly, conventional techniques in which an additional high-temperature thermal process is performed for a long period of time may degrade the device characteristics. For example, slippage or warpage may occur in the wafer. Moreover, the manufacturing cost may increase. Also, in such a case, metal contaminants, and particularly iron (Fe), which are trapped by the oxygen precipitates in the bulk region, may be released into the DZ by a subsequent process, so that the released contaminants can act as a leakage source.
FIG. 3 is a diagram illustrating a redrawn oxygen precipitate concentration profile of a wafer fabricated by another conventional method, which is disclosed in FIG. 1A of U.S. Pat. No. 5,401,669. In particular, FIG. 3 is the oxygen precipitate concentration profile of a wafer with respect to the depth of the wafer, resulting from a rapid thermal annealing process on a wafer carried out in a nitrogen atmosphere, and subjecting the wafer to subsequent heat treatment. However, as can be seen from FIG. 3, neither the DZ near the surface of the wafer nor sufficient oxygen precipitates in the bulk region may be obtained by this conventional method.
Embodiments of the present invention provide a silicon wafer having a controlled vertical distribution of oxygen precipitates which can act as intrinsic gettering sites. In particular, the oxygen precipitate concentration profile from the top surface, in which an active region of a semiconductor device may be formed, to the bottom surface of the silicon wafer, comprises first and second peaks at first and second predetermined depths from the top and bottom surfaces of the wafer, respectively. Also, a Denuded Zone (DZ) is included between the top surface of the wafer and the first peak and between the bottom surface of the wafer and the second peak. The oxygen precipitate concentration profile also has a concave region between the first and second peaks, which can correspond to a bulk region of the wafer.
Moreover, in embodiments of the invention, the denuded zone between the bottom surface of the wafer and the second peak includes therein at least one region of slip dislocation, whereas the denuded zone between the top surface of the wafer and the first peak is free of slip dislocation therein. In other embodiments, the silicon wafer also includes a plurality of Shallow Trench Isolation (STI) regions in the denuded zone, between the top surface of the wafer and the first peak, and that are free of STI slip. In yet other embodiments, the oxygen precipitate concentration profile includes first and second peaks, a denuded zone and a concave region between the first and second peaks, as was described above. A plurality of STI regions are included in the denuded zone, between the top surface of the wafer and the first peak which is close to the STI regions, that have an STI slip that is reduced compared to same STI regions in the silicon wafer that oxygen precipitates are present far away from the STI region in FIG. 2.
In some embodiments of the invention, the oxygen precipitate concentration profile is symmetrical with respect to a central surface of the silicon wafer that is centrally located between the top and bottom surfaces. Thus, for example, the first and second predetermined depths are the same. However, in other embodiments, the profile need not be symmetrical, such that, for example, different depths may be provided for the first and second peaks. Also, in some embodiments of the invention, the depth of the denuded zones is in the range of about 5 xcexcm to about 40 xcexcm from each surface of the silicon wafer, such that the active region of the semiconductor device is formed to a sufficient depth. In other embodiments of the invention, the oxygen precipitate concentrations at the first and second peaks are at least about 1xc3x97109 cmxe2x88x923, and oxygen precipitate concentration in the bulk region between the first and second peaks is at least about 1xc3x97108 cmxe2x88x923. In still other embodiments, a lowest oxygen precipitate concentration in the concave region is at least an order of magnitude lower than a highest oxygen precipitate concentration in the first and second peaks.
Silicon wafers according to other embodiments of the present invention include a controlled distribution of oxygen precipitate nucleation centers, for example vacancies, which can produce oxygen precipitate concentration profiles described above through subsequent thermal treatment. The vacancy concentration profile comprises first and second peaks at first and second predetermined depths from the top and bottom surfaces of the wafer, respectively. Also, the vacancy concentration remains at a predetermined concentration, which is lower than a critical concentration to make the DZ, between the top surface of the wafer and the first peak and between the bottom surface of the wafer and the second peak. The vacancy concentration profile has a concave region between the first and second peaks. In some embodiments, the denuded zone between the bottom surface of the wafer and the second peak includes therein at least one region of slip, whereas the denuded zone between the top surface of the wafer and the first peak is free of slip dislocation therein. In other embodiments, a plurality of STI regions are included in the denuded zone between the top surface of the wafer and the first peak, and having STI slip that is reduced compared to same STI regions in the silicon wafer that does not include the oxygen precipitate nucleation centers described above. Symmetrical or asymmetrical profiles may be provided.
According to method embodiments of the present invention, Rapid Thermal Annealing (RTA) is performed on a silicon wafer in an atmosphere of a gas mixture comprising a gas which has a vacancy injection effect and a gas which has an interstitial silicon injection effect on the top and bottom surfaces of the silicon wafer, and between about 1100xc2x0 C. and about 1200xc2x0 C., to generate nucleation centers, which act as oxygen precipitate growth sites during subsequent heat treatment, such that the nucleation center concentration profile from the top surface to the bottom surface of the wafer comprises first and second peaks at first and second predetermined depths from the top and bottom surfaces of the wafer, respectively. Also, the nucleation center concentration remains at a predetermined concentration, which is lower than a critical concentration to make the DZ, between the top surface of the wafer and the first peak and between the bottom surfaces of the wafer and the second peak. Finally, the nucleation center profile has a concave region between the first and second peaks, which corresponds to a bulk region of the wafer. Symmetrical or asymmetrical profiles may be provided.
In yet other embodiments, the RTA is performed on a silicon wafer in an atmosphere of a gas mixture comprising ammonia (NH3) and argon (Ar), to generate nucleation centers, which act as oxygen precipitate growth sites during subsequent heat treatment, such that the nucleation center concentration profile from the top surface to the bottom surface of the wafer may be as described above. In yet other embodiments, the RTA is performed between about 1100xc2x0 C. and 1150xc2x0 C. In still other embodiments, the RTA is performed at a temperature of about 1120xc2x0 C. In other embodiments, the RTA is performed for at least about five seconds. In still other embodiments, the RTA is preceded by rapidly heating the atmosphere comprising ammonia and argon, at about 50xc2x0 C. per second.
According to still other method embodiments of the present invention, a silicon wafer is manufactured by performing RTA on a silicon wafer having a top surface and a bottom surface in an atmosphere comprising argon and ammonia, for at least about five seconds and at between about 1100xc2x0 C. and about 1200xc2x0 C. In other embodiments, the RTA is performed at between about 1100xc2x0 and about 1150xc2x0 C. In still other embodiments the RTA is performed at about 1120xc2x0 C. In yet other embodiments, prior to performing the RTA, oxygen is purged from the atmosphere and sensing may be performed to determine that less than a predetermined concentration of oxygen is present in the atmosphere. Moreover, in other embodiments, prior to performing the RTA, heating of the atmosphere is increased at about 50xc2x0 C. per second, for example from about 800xc2x0 C. to between about 1100xc2x0 C. and about 1150xc2x0 C. Moreover, after performing the RTA, the heating may be decreased by between about 10xc2x0 C. per second and about 70xc2x0 C. per second, for example to about 800xc2x0 C. In yet other embodiments, after decreasing the heating, ammonia may be purged from the atmosphere.
According to other method embodiments of the present invention, a plurality of silicon wafers are manufactured by sequentially performing an RTA process on a series of silicon wafers in an RTA chamber in an atmosphere comprising argon and ammonia, and at below a temperature that causes sublimation of silicon dioxide from the series of silicon wafers onto the RTA chamber. The RTA may be performed under any of the conditions that were described above. In other embodiments, silicon wafers may be sequentially processed for up to six months or more without cleaning the RTA chamber of silicon dioxide.
According to other method embodiments, heat treatment is performed after the RTA to produce an oxygen precipitate concentration profile from the top surface to the bottom surface of the wafer, which comprises first and second peaks at first and second predetermined depths from the top and bottom surfaces of the wafer, respectively, a DZ between the top surfaces of the wafer and the first peak and between the bottom surface of the wafer and the second peak, and a concave region between the first and second peaks. Symmetrical or asymmetrical profiles may be provided.
In other embodiments of the invention, a silicon wafer that is subject to an RTA process according to embodiments of the present invention may be manufactured from an ingot which is pulled from molten silicon in a hot zone furnace according to an ingot pulling rate profile where the pulling rate of the ingot is high enough so that formation of interstitial agglomerates is prevented, but low enough so that formation of interstitial agglomerates is prevented, and the formation of vacancy agglomerates is prevented.
In still other embodiments of the invention, a silicon wafer that is subject to an RTA process according to embodiments of the present invention may be manufactured from an ingot which is pulled from a molten silicon in a hot zone furnace according to an ingot pulling rate profile, where the pulling rate of the ingot is high enough so that vacancy agglomerates are formed through the diameter of the ingot without forming interstitial agglomerates.
According to other embodiments of the invention, a Czochralski puller for growing a monocrystalline silicon ingot includes a chamber enclosure, a crucible in the chamber enclosure that holds molten silicon, a seed holder in the chamber enclosure adjacent the crucible to hold a seed crystal, and a heater in the chamber enclosure surrounding the crucible. A ring-shaped heat shield housing also is provided in the chamber enclosure including inner and outer heat shield housing walls that are separated from each other, and a heat shield housing top and a heat shield housing bottom which connect the inner and outer heat shield housing walls, the heat shield housing top sloping upwards from the inner heat shield housing wall to the outer heat shield housing wall, and the heat shield housing bottom sloping downwards from the inner heat shield housing wall to the outer heat shield housing wall. The ring-shaped heat shield housing also includes a notch therein at an intersection of the outer sheet housing wall and the heat shield housing bottom. A support member supports the heat shield housing within the crucible.
According to other embodiments, the heat shield housing bottom includes a first portion adjacent the inner heat shield housing wall that slopes downward from the inner heat shield housing wall toward the outer heat shield housing wall. The heat shield housing bottom also includes a second portion adjacent the outer heat shield housing wall that slopes downward from the outer heat shield housing wall toward the inner heat shield housing wall.
Czochralski pullers according to embodiments of the invention also pull the seed holder from the crucible to grow the molten silicon into the cylindrical monocrystalline silicon ingot, which grows along and around its central axis in a cylindrical shape and forms an ingot-molten silicon interface with the molten silicon. At least one of the lengths of the inner and outer heat shield housing walls of the heat shield housing, the slope angles of the heat shield housing top and first and second portions, the distance between the ingot and the inner heat shield housing wall, the distance between the crucible and the outer heat shield housing wall, the distance between the molten silicon and the inner heat shield housing wall and the location of the heat shield plate are selected such that the pulled ingot is cooled at a rate of at least 1.4xc2x0 K/min based on the temperature of the ingot at the center thereof, from the temperature at the ingot-molten silicon interface to a predetermined temperature of the ingot.